1. Field of the Invention
The present invention relates to a semiconductor device and a method of forming the same. More particularly, the present invention relates to a fin type transistor capable of preventing a short channel effect, reducing a leakage current, and reducing a junction capacitance in source/drain regions, and a method of forming the transistor.
2. Description of the Related Art
As the semiconductor industry rapidly develops, the semiconductor devices have minute sizes and improved degree of integration. Since the semiconductor devices have minute sizes, structures of the semiconductor devices also have minute dimensions. For example, the size of an active region of the semiconductor device greatly decreases so that a channel length of the semiconductor device also decreases.
When a channel length of a transistor is reduced, source/drain regions of the transistor may be greatly affected by an electric field in depletion layers adjacent to the source/drain regions. This phenomenon is referred to as a short channel effect. Also, a depletion layer adjacent to the drain region is extended in proportional to an augmentation of a drain voltage so that the depletion layer adjacent to the drain region is closely extended to a depletion layer adjacent to the source region. As a result, when the channel length is reduced, the depletion layer adjacent to the drain region is connected to the depletion layer adjacent to the source region. Since an electric field in the drain region affects the source region, an electric potential for diffusing electrons in the source region is lowered. Thus, although the channel region may not be formed between the source/drain regions, a current flows between the source/drain regions. This phenomenon is referred to as punch-through.
To overcome the above-mentioned problems, various methods for reducing sizes of semiconductor devices while improving characteristics of the semiconductor devices have been studied and developed. For example, there have been developed a vertical fin type transistor, a fully depleted lean-channel transistor (DELTA), a transistor having a gate all around (GAA) structure, etc.
An exemplary conventional fin type transistor is disclosed in U.S. Pat. No. 6,413,802. The fin type transistor includes thin fin shape channels disposed in parallel on a silicon-on-insulator (SOI) substrate. The fin shape channels are positioned between source/drain regions. A gate electrode extends along upper faces and sidewalls of the channel fins. In the conventional fin type transistor, since the gate electrode is formed on both sides of the fin shape channels, an effective area of the gate electrode is controlled by both sides of the fin shape channels, thereby reducing a short channel effect.
However, since the fin shape channels are arranged along a direction parallel to the gate electrode, the channel region and the source/drain regions may have relatively wide areas. Also, since the number of the channels is relatively large, a leakage current and a junction capacitance in the source/drain regions may be increased.
An exemplary DELTA is disclosed in U.S. Pat. No. 4,996,574. This transistor includes a channel layer for forming a channel region. The channel layer having a uniform width is vertically protruded from a substrate. A gate electrode encloses the protruded portion of the channel layer. Thus, a height of the protruded portion of the channel layer substantially corresponds to a width of the channel layer. Also, a width of the protruded portion substantially corresponds to a thickness of the channel layer. In this transistor, since both sides of the channel layer may be utilized, the width of the channel layer may be about doubled so that a reverse narrow width effect may be prevented. Further, when the width of the protruded portion is reduced, depletion layers formed on both sides of the channel layer may be overlapped to increase a conductivity of the channel layer.
However, when the DELTA is formed on a bulk silicon substrate, the bulk silicon substrate is processed to have a protruding portion that serves as a channel region. After an oxidation prevention layer covers the protruding portion, the bulk silicon substrate is oxidized. If the bulk silicon substrate is excessively oxidized, a portion of the bulk silicon substrate adjacent to the protruding portion is oxidized by oxygen because the oxidation prevention layer is formed on the protruding portion only. Hence, the protruding portion may be separated from the bulk silicon substrate. If the protruding portion is spaced apart from the bulk silicon substrate, a channel region of the DELTA may be greatly reduced and also the bulk silicon substrate may be greatly damaged due to a stress generated in the oxidation of the bulk silicon substrate.
On the contrary, when the DELTA is formed on a silicon-on-insulator (SOI) substrate, a channel region of the DELTA is formed to have a narrow width by partially etching the SOI substrate. Thus, the above problem caused by the excessive oxidation may be prevented when the SOI substrate is oxidized. Here, the width of the channel region is determined in accordance with a thickness of a silicon layer of the SOI substrate. However, because the SOI substrate, particularly a fully depletion-type SOI substrate having a thickness of hundreds of angstroms, the DELTA may have the channel region with an extremely narrow width.
Further, the DELTA does not make direct contact with the silicon substrate. Namely, the DELTA has a floating body. Thus, a floating body effect such as a parasite bipolar-induced breakdown or a latch up may be caused because holes may be accumulated at a rear interface of the SOI substrate.